
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--- not purely combinatorial/sequential.
--- entity is here mainly for the sake of abstraction
entity div_preprocess_layer is
	PORT (
	clk : in STD_LOGIC;
	denominator : in STD_LOGIC_VECTOR(31 downto 0);
	is_signed : in STD_LOGIC;
	
	out_m_1 : out STD_LOGIC_VECTOR(34 downto 0);
	out_m_2 : out STD_LOGIC_VECTOR(34 downto 0);
	out_m_3 : out STD_LOGIC_VECTOR(34 downto 0)
	);
end div_preprocess_layer;

architecture Behavioral of div_preprocess_layer is
	component latched_34_adder is
		PORT (
		clk : in STD_LOGIC;
		input1 : in STD_LOGIC_VECTOR(34 downto 0);
		input2 : in STD_LOGIC_VECTOR(34 downto 0);
		
		output : out STD_LOGIC_VECTOR(34 downto 0) -- guaranteed to not exceed 
		);
	end component;

	signal adder_input_1 : STD_LOGIC_VECTOR(34 downto 0);
	signal adder_input_2 : STD_LOGIC_VECTOR(34 downto 0);
	
	signal sign_extended: STD_LOGIC_VECTOR(34 downto 0);
	
begin
	preprocess_adder : latched_34_adder 
	port map 
	(
		clk => clk,
		input1 => adder_input_1,
		input2 => adder_input_2,
		
		output => out_m_3
	);
	
	process(denominator, is_signed)
	begin
		if (is_signed = '1' and denominator(31) = '1') then
			sign_extended <= "111" & denominator;
		else
			sign_extended <= "000" & denominator;
		end if;
	end process;
	
	out_m_1 <= sign_extended;
	adder_input_1 <= sign_extended;
	out_m_2 <= sign_extended(33 downto 0) & "0";
	adder_input_2 <= sign_extended(33 downto 0) & "0";
	

end Behavioral;

